1. Field of the Invention
The present invention pertains to integrated signal processing circuits suitable for application to circuits for carrying out convolution calculations.
2. Related Art
Convolution calculation circuits are often employed in devices such as digital audio equipment wherein various types of filtering operations are applied to an audio signal, including equalization, reverberation effect processing and the like. As an example of this kind of circuit, a block diagram illustrating the fundamental makeup of an N stage convolution calculation circuit is shown in FIG. 3, where N is an integral value. In the illustrated circuit, a digital signal is input periodically at a sampling cycle length given by .tau., whereupon the supplied signal is sequentially delayed in serially connected delay circuits D.sub.1, D.sub.2 , . . . D.sub.N-1. The above mentioned delay circuits D.sub.1, D.sub.2 , . . . D.sub.N-1 comprise registers, where each respective register is of a fixed bit width. To each of these registers, a clock pulse is supplied periodically at the above mentioned sampling cycle length .tau.. Accordingly, at the point in time when sample signal X.sub.n is input to delay circuit D.sub.1, the sample signal output from delay circuit D.sub.1 at that point in time is sample signal X.sub.n-1 which was input at a point time .tau. previously, the sample signal output from delay circuit D.sub.2 when sample signal X.sub.n is input to delay circuit D.sub.1 is sample signal X.sub.n-2 which was input at a point in time 2.tau. previously, and the sample signal output from delay circuit D.sub.N-1 when sample signal X.sub.n is input to delay circuit D.sub.1 is sample signal X.sub.n-N-1 which was input at a point in time (N-1).tau. previously. Input signal Xn, as well as the output signal X.sub.n -1, X.sub.n-2 , . . . N.sub.n-N+ of each delay circuit D.sub.1 D.sub.2 , . . . D.sub.N-1, respectively, are each provided to a respective multiplier circuit M.sub.0, M.sub.1 , . . . M.sub.N-1, wherein each supplied signal is multiplied by a corresponding multiplication coefficient C.sub.0, C.sub.1 , . . . C.sub.N-1, the output of each multiplication then being supplied to adder A wherein the result of all of the multiplication operations are added together. In this way, within the described convolution calculation circuit, a plurality of convolution calculations are carried out, after which the results of all of the calculations are summed in adder A, the result of which is output as digital data Y.sub.n. This operation is mathematically expressed in Equ. 1 below: ##EQU1##
When an attempt is made to implement the above described convolution calculation circuit with a great number of convolution calculations using LSI (large scale integration) techniques, the total number of components inevitably becomes unmanageably large, thus making such an implementation in a single LSI integrated circuit quite difficult from a practical point of view.
Methods exist for applying LSI techniques to convolution calculation circuits having a great number of calculation stages, wherein two or more signal processing LSI integrated circuits are fabricated, each integrated circuit corresponding to a continuous series of calculation stages. With such an implementation, the entire series of delay stages over which the convolution calculations occur is divided into two or more continuous blocks along the time axis with respect to time delay. The calculations of each of these blocks are allocated to a corresponding one of the above mentioned signal processing LSI integrated circuits. By cascade connecting the signal processing LSI integrated circuits, the entire convolution calculation circuit is formed.
In FIG. 4, an example of this kind of convolution calculation circuit is shown. The illustrated circuit is made up of three signal processing LSI integrated circuits LSI 11, LSI 12 and LSI 13, each having M convolution calculation stages, where M is an integral value, thus comprising 3M convolution calculation stages for the circuit as a whole. All elements in FIG. 4 corresponding to elements in the circuit of FIG. 3 described above will retain the original identifying numeral.
To describe an example of the operation of the circuit shown in FIG. 4, when a signal is input at input port DI of signal processing LSI integrated circuit LSI 11, it first passes through delay circuit D.sub.0 where it is delayed by a single sampling interval .tau., after which it then passes successively through each of the delay circuits D.sub.1, D.sub.2 , . . . D.sub.N-1, as well as through multiplier circuits M.sub.0, M.sub.1, to then be summed in adder A.sub.11, just as was described above for the circuit of FIG. 3.
In the circuit presently under discussion, delay circuit D.sub.0 acts as an interface and provides an initial delay for the sampling signal after it passes through input port DI. In the same way, delay circuits DJ.sub.01, DJ.sub.02, DK.sub.01, and DK.sub.02 act to delay incoming and outgoing data for signal processing LSI integrated circuit LSI 11.
In addition to the results of each of the multiplication operations carried out in multiplication circuits M.sub.0, M.sub.1 , . . . M.sub.M-1, adder A.sub.1 1 also includes in the calculated sum any signal provided to convolution calculation result input port SI after first passing through delay circuit DK.sub.01 where the input signal is first delayed by a single sampling interval .tau. before it is supplied to adder A.sub.11. In the case of signal processing LSI integrated circuit LSI 11, no signal is supplied to convolution calculation result input port SI since it is the first signal processing circuit in the cascade. The result of the addition operation output from adder A.sub.11 is then supplied to delay circuit DK.sub.02 where the input signal is first delayed by a single sampling interval .tau., after which it is output at convolution calculation result output port SO as the result of the convolution calculations carried out in signal processing LSI integrated circuit LSI 11. Thus output, the signal is then supplied to convolution calculation result input port SI of signal processing LSI integrated circuit LSI 12, the next integrated circuit in the cascade. The signal thus supplied to convolution calculation result input port SI of signal processing LSI integrated circuit LSI 12 is then further delayed in delay circuit DK.sub.11 by a single sampling interval .tau..
On the other hand, the output signal from delay circuit D.sub.M-1 is signal processing LSI integrated circuit LSI 11 passes through delay circuits DJ.sub.01 and DJ.sub.02 thereby causing it to be delayed by two sampling intervals .tau. before being output at delayed signal output port DO. From delayed signal output port DO, the signal is supplied to the following signal processing stage, signal processing LSI integrated circuit LSI 12 via calculation result input port SI. As described above, in signal processing LSI integrated circuit LSI 11, the sum of the delay intervals in delay circuits DJ.sub.01 and DJ.sub.02 and the sum of the delay intervals in delay circuits DK.sub.01 and DK.sub.02 are equal. In this way, the phase of the delayed sampling signal supplied from signal processing LSI integrated circuit LSI 11 to signal processing LSI integrated circuit LSI 12 remains synchronized with the phase of the result of the convolution calculations.
Signal processing LSI integrated circuit LSI 12 which is connected with the last stage of signal processing LSI integrated circuit LSI 11 is of an analogous structure to signal processing LSI integrated circuit LSI 11. However, in the case of signal processing LSI integrated circuit LSI 12, the multiplication coefficients by which each successively delayed sampling signal is multiplied are designated as multiplication coefficients C.sub.M, C.sub.M+1 , . . . C.sub.2M-1. Thus, in signal processing LSI integrated circuit LSI 12, the signal input at calculation result input port SI from signal processing LSI integrated circuit LSI 11 is successively delayed in delay circuits D.sub.M, D.sub.M+1 , . . . D.sub.2M-1, and each successively delayed signal is multiplied in a respective multiplication circuit M.sub.M, M.sub.M+1 , . . . M.sub.2M-1 by a corresponding multiplication coefficient C.sub.M, C.sub.M+1 , . . . C.sub.2M-1, just as described for signal processing LSI integrated circuit LSI 11 above. The results of these multiplication operations are then summed in adder A.sub.12 , along with the first stage convolution calculation signal input at calculation result input port SI after it has been delayed in delay circuit DK.sub.11. The result of this addition operation is then output at calculation result output port SO after first being delayed by a single sampling interval .tau. in delay circuit DK.sub.12. Thus having undergone convolution calculations in signal processing LSI integrated circuit LSI 11 and LSI 12, the signal output from calculation result output port SO of signal processing LSI integrated circuit LSI 12 is supplied to the calculation result input port SI of the following signal processing stage, signal processing LSI integrated circuit LSI 13. In the present example, the structure of signal processing LSI integrated circuit LSI 13 is analogous to that of the previously described signal processing LSI integrated circuits LSI 11 and LSI 12.
In the following, with reference to FIG. 5, the operation of this conventional convolution calculation circuit will be described. At a given point in time t.sub.0, a sample signal X.sub.n is supplied to input port DI (node N.sub.0) of the first stage signal processing circuit, signal processing LSI integrated circuit LSI 11. Because the sample signal output from signal processing LSI integrated circuit LSI 11 at delayed signal port DO (node 1) at time t.sub.0 has traversed M+2 delay circuits, this signal is sample signal X.sub.n-M-2 which was input at input port DI (node N.sub.0) at a point in time (M+2).tau. earlier than time t.sub.0. In the same way, because the sample signals output from signal processing LSI integrated circuits LSI 12 and LSI 13 at their respective delayed signal output ports DO (nodes N.sub.2 and N.sub.3 respectively) have traversed M+2 delay circuits in each of these integrated circuits, at time t.sub.0, the signal at node N.sub.2 is sample signal X.sub.n-2M-4, and that at node N.sub.3 is sample signal X.sub.n-3M-6.
At time t.sub.0, sample signals X.sub.n-1, X.sub.n , . . . X.sub.n-M are output from delay circuits D.sub.0, D.sub.1 , . . . D.sub.M-1, respectively, and their aggregate sum is determined in adder A.sub.11. Accordingly, at time t.sub.0, the signal value at node N.sub.1a is given by Equ. 2 below: ##EQU2## Since two delay circuits are interposed in the connection between adders A.sub.11 and A.sub.12, the signal supplied to adder A.sub.12 from adder A.sub.11 at time t.sub.0 is the signal output from adder A.sub.11 at a point in time 2.tau. earlier than time t.sub.0, the value of which is given by Equ. 3 below: ##EQU3## Sample signals X.sub.n-M-3, X.sub.n-M-2 , . . . X.sub.n-2M-2 are output from delay circuits D.sub.M, D.sub.M+1 , . . . D.sub.2M-1, respectively, at time t.sub.0. Thus, the value of the signal present at node N.sub.2a at time t.sub.0, which is the result of adding the results obtained by multiplying each of sample signals X.sub.n-M-3, X.sub.n-M-2 , . . . X.sub.n-2M-2 by a respective multiplication coefficient in a respective multiplication circuit, and additionally adding the signal supplied from adder A.sub.11 in adder A.sub.12, is given by Equ. 4 below: ##EQU4## The result of the convolution calculations carried out in signal processing LSI integrated circuit LSI 12, as given by Equ. 4 above, is then employed in the convolution calculations carried out in the following stage, signal processing LSI integrated circuit LSI 13 after having been delayed by two sampling intervals .tau.. After undergoing further convolution calculation processing in signal processing LSI integrated circuit LSI 13, which is analogous to that described for signal processing LSI integrated circuits LSI 11 and LSI 12, the final result of the convolution calculations over the three stages is output at calculation result output port SO of signal processing LSI integrated circuit LSI 13 after having been delayed by an additional sampling interval .tau.. Thus, the value of the signal at node N.sub.4 at time t.sub.0 is given by Equ. 5 below: ##EQU5## It can therefore be seen that at time t.sub.0, the convolution calculation result output at node N.sub.4 represents the result of convolution calculations involving 3M sample signals from sample signal X.sub.n-6 which was input a point in time 6.tau. prior to time t.sub.0 and all sample signals input up to and including sample signal X.sub.n input at time time t.sub.0. Accordingly, and as is shown in FIG. 5, when a sample signal X.sub.n is input into the conventional convolution calculation circuit shown in FIG. 4 at time t.sub.0, at time t.sub.6 six sampling intervals .tau. after time t.sub.0, the result of convolution calculations involving sample signals X.sub.n, X.sub.n-1 , . . . X.sub.n-3M+1 is output at node N4.
In the above description where three integrated circuits are cascade connected, to further expand the system by adding fourth and fifth stages, the number of delay circuits which a signal must traverse and which are not directly involved in the convolution calculations (for example, delay circuits DK.sub.01 and DK.sub.02 in signal processing LSI integrated circuit LSI 11) increases in proportion to the number of calculation stages. Thus, in conventional convolution calculation circuits in which two or more signal processing LSI integrated circuits are cascade connected, with each added signal processing LSI integrated circuit, the amount of time which is required for signals to pass through delay elements not directly involved in the convolution calculations increases. For this reason, the elapsed time between when a signal is input and when calculation results involving that signal are output becomes quite long, which is a significant problem for many of the applications of this type of circuit. For example, in the case of an electronic musical instrument, for the individual operating such a musical instrument, any noticeable delay between the actions of the operator and the time at which the effect is produced in the musical output is clearly undesirable.